1/4 rev. b structure silicon monolithic integrated circuit product name pcm codec ic for cellular phone product no. BU8920GU physical dimentions figure1 (vcsp85h2) features 16bit linear ? /a-law codec built-in pll circuit for system clock generation support for below frequency about pcm data transmission clock. /a-law 64khz - 2048 khz linear 128 khz -2048 khz built-in output amplifier for line drives (600 ) power down control using nrst pin absolute maximum ratings parameter symbol rating unit digital supply voltage analog supply voltage input voltage for digital terminal ?? input voltage for analog terminal ??? input current power dissipation *1 storage temperature range (*1) note: reduce to 2.5mw/ when ta = 25 or above recommended operating power supply voltage and temperature range parameter symbol rating unit min typ max digital supply voltage analog supply voltage operating temperature range opr - this product is not designed to protect itself against radioactive rays.
2/4 rev. b electrical characteristics unless otherwise noted, ta = 25 avdd=2.8 dvdd=1.8v fsync=8khz dclk=256khz. parameter symbol specified value unit condition min typ max current consumption standby current consumption idd1 - 0.1 3.0 ua nrst=dvss and fsync,dclk=dvss full operation idd2 - 2.5 3.8 ma nrst,bst=dvdd, no input signal dc characteristics digital h level input voltage vih dvdd 0.75 - 4.5 digital l level input voltage vil - 0.3 - dvdd 0.25 digital h level input current iih - - 1 ua vih=dvdd digital l level input current iil - - -1 ua vil=dvss digital h level output voltage voh dvdd 0.8 - ioh= -1ma digital l level output voltage vol - dvdd 0.2 iol= 1ma unless otherwise noted, ta=25c,avdd=2.7 3.1 ,? 1.65 1.95 ,fsync=8khz,dclk=256khz,and linear mode. parameter symbol condition s p ecified value unit min typ max transmit signal-to-distortion ratio (aux1in pcmout) 1020hz 2,3 0dbm0 45 - - -30dbm0 35 - - -40dbm0 29 - - -45dbm0 24 - - receive signal-to-distortion ratio (pcmin audout) 1020hz 2 0dbm0 45 - - -30dbm0 35 - - -40dbm0 29 - - -45dbm0 24 - - transmit gain tracking ( 1 ) 1020hz reference level=-10 0 2,3 +3.00.5dbm0 -3.0 - 3.0 +0.5 -40dbm0 -0.3 - 0.3 -40 -50dbm0 -0.6 - 0.6 -50 -55dbm0 -1.6 - 1.6 receive gain tracking (pcmin audout) 1020hz reference level=-10 0, 2 +3.0 -40dbm0 -0.3 - 0.3 -40 -50dbm0 -0.6 - 0.6 -50 -55dbm0 -1.6 - 1.6 transmit reference level 1020hz 0dbm0 2 aux1in pcmout 0.375 0.500 0.667 receive reference level 1020hz 0dbm0 2 pcmin audout 0.400 0.475 0.564 transmit gain loss relative to frequency (aux1in pcmout) 1020hz 0.06khz 24 - - db 0.2khz 0 - 2.5 0.30.4khz -0.3 - 0.5 0.43.0khz -0.3 - 0.3 3.4khz -0.3 - 0.9 3.6khz 0 - - 3.78khz 6.5 - - receive gain loss relative to frequency (pcmin audout) 1020hz 0.06khz 24 - - db 0.2khz 0 - 2.5 0.32.8khz -0.3 - 0.3 2.83.0khz -0.3 - 0.5 3.4khz -0.3 - 0.9 3.6khz 0 - - 3.78khz 6.5 - - transmit noise level v ntx aux1in= agnd level. 2 -- -76 dbv receive noise level v nrx pcmin=?l?. usin g a-wei g ht filter. - - -85 dbv 2 using c-message filter 3 specified that 0dbm0 is 0.5vrms
3/4 rev. b physical dimentions (figure1) ball assignment vcsp85h2 23balls unit: mm block diagram (figure2) ball no ball name ball no ball name a1 avss c5 pcmsel a2 audout d1 frm2 a3 avdd d2 nrst a4 bgflt d3 dvdd a5 nc d4 pcmin b1 aux1in d5 dclk b3 pllcap e1 test b4 agnd e2 dsel b5 vref e3 bst c1 frm1 e4 dvss c2 nc e5 pcmout c4 fsync bu8920 lot no audout (a2) dclk (d5) + - pcm p to s pcmout (e5) fsync (c4) pcm s to p pcmin (d4) agnd (b4) vref (b5) nrst (d2) avdd (a3) avss (a1) bst (e3) pll pllcap (b3) dvss (e4) dvdd (d3) aux1in (b1) bgflt (a4) + - dac smf d to s bpf aaf s to d adc bpf bias system clock test (e1) dsel (e2) frm1 (c1) frm2 (d1) pcmsel (c5) : ball no power down control using only nrst. nrst = l : power down mode nrst = h : active mode nc : this ball is not connected with internal.
4/4 rev. b cautions on use (1) absolute maximum ratings an excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down devices, thus making impossible to identify br eaking mode such as a short circuit or an open circuit. if any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. (2) operating conditions these conditions represent a range within which charac teristics can be provided approx imately as expected. the electrical characteristics are guaranteed under the conditions of each parameter. (3) reverse connection of power supply connector the reverse connection of power supply connector can br eak down ics. take protective measures against the breakdown due to the reverse connection, such as mountin g an external diode between the power supply and the ic?s power supply terminal. (4) power supply line design pcb pattern to provide low impedance for the wiri ng between the power supply and the gnd lines.in this regard, for the digital block power supply and the analog bloc k power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. for the gnd line, give consideration to design the patterns in a similar manner. furthermore, for all power supply terminals to ics, mount a capacitor between the power supply and the gnd terminal. at the same time, in order to use an electrolytic capacito r, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. (5) gnd voltage make setting of the potential of the gnd terminal so that it will be maintained at the minimum in any operating state. furthermore, check to be sure no terminals are at a potential lower than the gnd voltage including an actual electric transient. (6) short circuit between terminals and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occu rs due to foreign matters entering between terminals or between the terminal and the power supply or the gnd terminal, the ics can break down. (7) operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. (8) inspection with set pcb on the inspection with the set pcb, if a capacitor is connected to a low-impedance ic terminal, the ic can suffer stress. therefore, be sure to discharge from the set pcb by each process. furthermore, in order to mount or dismount the set pcb to/from the jig for the inspection process, be sure to turn off the power supply and then mount the set pcb to the jig. after the completion of the inspection, be sure to turn off the power supply and then dismount it from the jig. in addition, for protection against static electricity, establish a ground fo r the assembly process and pay thorough attention to the transportation and the storage of the set pcb. (9)input terminals in terms of the construction of ic, parasitic elements are inevitably formed in relation to potential. the operation of the parasitic element can cause interference with circuit operat ion, thus resulting in a malfunction and then breakdown of the input terminal. therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the gnd respectively, so t hat any parasitic element will operate. furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the ic. in addition, even if the power supply voltage is applied, apply to the input terminals a vo ltage lower than the power supply voltage or within the guaranteed value of electrical characteristics. (10) ground wiring pattern if small-signal gnd and large-current gnd are provided, it will be recommended to separate the large-current gnd pattern from the small-signal gnd pattern and establish a sing le ground at the reference point of the set pcb so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal gnd. pay attention not to cause fluctuatio ns in the gnd wiring pattern of external parts as well. (11) external capacitor in order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the nominal capacitance due to dc bias and changes in the capacitance due to temperature, etc. (12) others in case of use this lsi, please peruse some other detail documents, we called ,technical note, functinal description, application note.
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